1. Field of the Invention
The present invention relates to a semiconductor memory device having an error correcting circuit and a method for correcting an error. More particularly, the present invention relates to a semiconductor memory device having an error correcting circuit for detecting and correcting an error in the information read from each memory cell incorporated in a semiconductor memory device and a method for correcting an error.
2. Description of the Prior Art
FIG. 1 is a schematic block diagram showing a conventional MOS dynamic RAM.
Referring to FIG. 1, a description is made of the whole structure of the conventional MOS dynamic RAM. A row address signal is externally applied to a row address buffer 1. The row address buffer 1 stores the row address signal and applies the same to a row decoder 2. The row decode 2 decodes the row address signal to specify a column address of a memory cell array 3. On the other hand, a column address signal is externally applied to a column address buffer 4. The column address buffer 4 stores the column address signal and applies the same to a column decoder 5. The column decoder 5 decodes and applies the column address signal to the memory cell array 3 through a sense amplifier 6 to specify a row address of the memory cell array 3.
A sense signal generating circuit 7 and an I/O circuit 9 are connected to the sense amplifier 6. The sense signal generating circuit 7 outputs a signal for driving the sense amplifier. The input/output of the I/O circuit 9 is switched by an output control circuit 8. More specifically, when the I/O circuit 9 is switched to the input side, the inputted data is stored in a predetermined addressed memory cell in the memory cell array through the sense amplifier 6. When the I/O circuit 9 is switched to the output side, data is read from a predetermined addressed memory cell and outputted from the sense amplifier 6 through the I/O circuit 9. The memory cell array 3 comprises n.times.m memory cells.
FIG. 2 is a diagram showing in greater detail a memory cell in the MOS dynamic RAM shown in FIG. 1. Referring to FIG. 2, a description is made of a memory cell of the conventional MOS dynamic RAM. Memory cells MC.sub.0, .sub.0 to MC.sub.63, .sub.63 constitute a memory cell array with 64 rows and 64 columns, each of cells being a dynamic type of one-transistor one-capacitance type formed of an N channel MOS transistor Q and capacitance C.sub.S. Word lines W.sub.0 to W.sub.63 are connected to each of memory cells MC.sub.0, .sub.0 to MC.sub.63, .sub.63 and each of word lines W.sub.0 to W.sub.63 is selected by a row decoder 2 in response to a row address signal externally applied. Bit line pairs of the BL.sub.0 and BL.sub.0 to BL.sub.63 and BL.sub.63 are connected to each of memory cells MC.sub.0, .sub.0 to MC.sub.63, .sub.63 in a column direction. Dummy word lines DW.sub.0 and DW.sub.1 are connected to dummy cells DM.sub.0, .sub.0 to DM.sub.63, .sub.1 and any dummy cell is selected by the dummy word lines DW.sub.0 and DW.sub.1.
Sense amplifiers SA.sub.0 to SA.sub.63 including P channel MOS transistors 61 and 62 and N channel MOS transistors 63 and 64 connected in a crossing manner are connected to the bit line pairs BL.sub.0 and BL.sub.0 to BL.sub.63 and BL.sub.63. Activation signals SP and SN generated from a sense signal generating circuit 7 are applied to each source of the P channel MOS transistors 61 and 62 and the N channel MOS transistors 63 and 64 comprised in the sense amplifiers SA.sub.0 to SA.sub.63.
The bit line pairs BL.sub.0 and BL.sub.0, and BL.sub.63 and BL.sub.63 are connected to I/O bus line pair I/O and I/O through N channel MOS transistors 10 to 13. Y signal lines Y.sub.0 to Y.sub.63 are applied from the column decoder 5 to the gates of the N channel MOS transistors 10 to 13. Conduction of the N channel MOS transistors 10 to 13 between bit line pairs BL.sub.0 and BL.sub.0 to BL.sub.63 and BL.sub.63 is controlled by the Y signal lines Y.sub.0 to Y.sub.63. A data output main amplifier 91 and a data input buffer 92 are connected to the I/O bus line pair I/O and I/O. The data output main amplifier 91 outputs the information from the I/O bus line pair I/O and I/O as a data output DO to outside during a reading cycle. The data input buffer 92 converts the level of a data input DI externally applied and applies them to the I/O bus line pair I/O and I/O as a complementary signal during a writing cycle.
Next, a description is made of the operation of the memory. During the reading cycle, assuming that, for example, the memory cell MC.sub.0, .sub.0 is selected, the row decoder 2 raises a potential of the word line W.sub.0 and the dummy word line DW.sub.0 and an electric charge stored in the storage capacitance C.sub.S is transferred to the bit line pairs BL.sub.0 and BL.sub.0 to BL.sub.63 and BL.sub.63 which have been previously charged to the same potential. For example, an electric charge representing information of the memory cell MC.sub.0, .sub.0 is transferred to the bit line BL.sub.0 and an electric charge of the dummy cell DM.sub.0, .sub.0 is transferred to the inverted bit line BL.sub.0 so as to generate a reference voltage.
When the sense amplifier activation signal SN becomes a low level and the activation signal SP becomes a high level, the sense amplifiers SA.sub.0 to SA.sub.63 are activated. More specifically, a minute difference of a signal voltage caused by an electric charge representing information transferred to the bit line pairs BL.sub.0 and BL.sub.0 to BL.sub.63 and BL.sub.63 is sensed and amplified. Then, a Y signal line (Y.sub.0 in this case) is selected in response to a column address signal which was externally applied to the column decoder 5 and the potential thereof is raised to cause a voltage of a complementary signal on the bit line pair BL.sub.0 and BL.sub.0 to be transferred to the I/O bus line pair I/O and I/O, respectively, amplified by the data output main amplifier 91 and outputted as the data output DO.
During the writing cycle, data is written to a desired memory cell through a path opposite to the reading cycle. More specifically, the level of the data input signal DI applied from the outside of the chip is converted by the data input buffer 92 and transmitted as a complementary signal to the I/O bus line pair I/O and I/O. If the Y.sub.0 signal line, for example, is selected by the column decoder 5, the complementary data input signal on the I/O bus pair I/O and I/O is transferred to the bit line pair BL.sub.0 and BL.sub.0. At this time, if the word line W.sub.0, for example, has been selected, the information is written in the memory cell MC.sub.0, .sub.0 on the intersecting point of the word line W.sub.0 and the bit line pair BL.sub.0 and BL.sub.0.
Meanwhile, the conventional MOS dynamic RAM was constituted as described above, the error detecting and correcting circuit was generally connected to the outside. If the error detecting and collecting circuit is contained in the chip, the error detecting and correcting circuit is connected to the output of the data output main amplifier 91 and the input of the data input buffer 92. Then, the data read from the memory cell array 3 is applied to the error detecting and correcting circuit through the I/O bus line pair I/O and I/O and the data output main amplifier 91 to detect and correct the error in the data and the error corrected data is written into the memory cell array 3 through the data input buffer 92 and the I/O bus line pair I/O and I/O. However, when the error is detected and corrected in this way, there is such disadvantage that it takes time to detect and correct the error in data.
In order to reduce time for detecting and correcting the error, the number of data bits useful for detecting the error is to increase at the same time, but if the bit number is increased, the number of the I/O bus line pair I/O and I/O is increased, so that chip area is also increased.
As another example of the MOS type dynamic RAM containing the error correcting circuit, there is "A Submicron 1M bit Dynamic RAM with a 4-Bit-at-a-Time Built-In ECC Circuit" IEEE JOURNAL OF SOLID-STATE CIRCUITS. Vol. SC-19, No. 5 OCTOBER 1984, which is proposed by Yamada, et al. However, this proposed correcting circuit of the dynamic RAM has a relatively complicated structure.